Received: from alice.unibel.by (PHIS_SERVER [10.1.1.1]) by mail.gsu.by with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2656.59) id SWH9VRJ7; Sat, 11 Oct 2003 09:48:25 +0300 Received: from leviathan.ele.uri.edu ([131.128.51.64]) by alice.unibel.by with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2655.55) id 4T036KQP; Sat, 11 Oct 2003 09:43:34 +0300 Received: from leviathan.ele.uri.edu (localhost [127.0.0.1]) by leviathan.ele.uri.edu (8.12.9/8.12.9) with ESMTP id h9B0S8a6019671 for ; Fri, 10 Oct 2003 20:28:08 -0400 (EDT) Received: (from majordom@localhost) by leviathan.ele.uri.edu (8.12.9/8.12.9/Submit) id h9B0S8oe019670 for tcca-list; Fri, 10 Oct 2003 20:28:08 -0400 (EDT) X-Authentication-Warning: leviathan.ele.uri.edu: majordom set sender to owner-tcca@ele.uri.edu using -f Received: from localhost (localhost [127.0.0.1]) by leviathan.ele.uri.edu (8.12.9/8.12.9) with ESMTP id h9B0S5a7019662 for ; Fri, 10 Oct 2003 20:28:05 -0400 (EDT) Date: Fri, 10 Oct 2003 20:28:05 -0400 (EDT) From: Qing Yang X-Sender: qyang@leviathan To: tcca@ele.uri.edu Subject: IEEE TCCA Email-Monthly Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=X-UNKNOWN X-MIME-Autoconverted: from QUOTED-PRINTABLE to 8bit by leviathan.ele.uri.edu id h9B0S7a6019667 Sender: owner-tcca@ele.uri.edu Precedence: bulk Reply-To: tcca@ele.uri.edu Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by leviathan.ele.uri.edu id h9B0S8a6019671 Welcome to IEEE TCCA Email-Monthly, Oct. 2003: 1. ISCA-2004: The 31st Annual International Symposium on Computer Archite= cture *June 19-23, 2004, Munich, Germany *Paper submission deadline: Nov 7, 2003=20 -CALL FOR PAPERS: http://isca.in.tum.de/ =20 2. NP3 - 2004: Workshop on Network Processors & Applications=20 *February 14-15, 2004, Madrid, Spain. *Workshop URL : http://www.cse.wustl.edu/NP3 *Paper submission deadline: November 3=20 -submitted by: Patrick Crowley =20 3. RAW 2004: The 11th Reconfigurable Architectures Workshop *April 26-27, 2004, Santa Fe, New Mexico =20 *Submission Deadline: Extended to October 20, 2003 -Submitted by: R. Vaidyanathan -CALL FOR PAPERS: http://www.ece.lsu.edu/vaidy/raw04/ 4. WEPA-1: 1st Workshop on Embedded Parallel Architectures *Saturday, Feb 14th, 2004, Madrid, Spain *Submission Deadline: Extended to Nov 23rd '03 -Submitted by: Jean-Luc Gaudiot, gaudiot@uci.edu -CALL FOR PAPERS: dragon.kayamba.com/~enric/wepa-1.htm 5. HAPCW 2003: High Availability and Performance Computing Workshop=20 *October 27, 2003, Eldorado Hotel - Santa Fe, New Mexico -Submitted by: Ben He -Workshop Site: http://cenit.latech.edu/hapcw2003 6. HiCOMB 2004: 3rd International Workshop On High Performance Computatio= nal=20 Biology *April 26, 2004, Eldorado Hotel, Santa Fe, NM *Submission deadline: December 1, 2003 -Submitted by: David A. Bader -CALL FOR PAPERS: http://www.cs.ucf.edu/~dcm 7. CAC '04: Workshop on Communication Architecture for Clusters=20 *April 26-30, 2004, Santa Fe, New Mexico Eldorado Hotel *Submission Deadline: October 30, 2003=20 -Submitted by: Nectarios Koziris -CALL FOR PAPERS: http://www.cis.ohio-state.edu/~cac 8. Interact 8: Workshop on Interaction between Compilers and Computer=20 Architectures * February 15, 2004, Madrid, Spain *Submission Deadline: November 23, 2003 -Submitted by: Gyungho Lee -CALL FOR PAPERS: http://api.ece.uic.edu/workshop/interact.htm ------- * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members,=20 send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20 ----------------------------------------------------------------------- Qing (Ken) Yang, Professor =09 Distinguished Engineering Professor e-mail: qyang@ele.uri.edu =20 Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 =20 University of Rhode Island Fax (401) 782-6422 =20 Kingston RI. 02881 http://www.ele.uri.edu/~qyang = =20 ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------- ISCA-2004 Call for Papers The 31st Annual International Symposium on Computer Architecture Munich, Germany, June 19-23, 2004 http://isca.in.tum.de/ --------------------------------------------------------------------- Papers are solicited for the 31st Annual International Symposium on Computer Architecture. Papers are being sought on all aspects of computer architecture, including (but not limited to) the following: * Processor architectures * Memory hierarchy subsystems * Multiprocessors and multicomputers * Storage and interconnect subsystems * Application-specific, reconfigurable, and embedded architectures * Power-efficient architecture * Dependable architectures * Impact of technology on architecture * Impact of application characteristics on architecture * Architectures for emerging technologies and applications * Performance/power evaluation and measurement of real systems The DEADLINE for abstract submissions (300 - 600 words) is OCTOBER 31, 2003 at 11.59PM PST (US). FULL PAPERS are due on November 7, 2003 at 11.59PM PST (US). NO EXTENSION WILL BE GRANTED!!! NOTIFICATION of acceptance/rejection will be given on FEBRUARY 17, 2004. FINAL VERSIONS of the accepted papers are due on MARCH 24, 2004. As in previous years, a series of tutorials and workshops will be held immediately preceding the symposium. Tutorial and workshop proposals will be accepted until November 14, 2003. If you wish to organize a tutorial (1/2 or 1 day), e-mail a proposal to the Tutorials Chair (Timothy Pinkston, tpink@charity.usc.edu), including title, brief description of topics to be covered, and bio of the speakers. If you wish to organize a workshop (1 or 2 days), e-mail a proposal to the Workshops Chair (Sally A. McKee, sam@csl.cornell.edu), including title, brief description of topics to be covered, and bio of the organizers. Notification of tutorial and workshop decisions will be emailed back to authors on December 15, 2003. Summary of important dates: Abstract submission deadline: Oct 31, 2003 Paper submission deadline: Nov 7, 2003 Workshop/tutorial proposal deadline: Nov 14, 2003 Workshop/tutorial proposal notification: Dec 15, 2003 Paper acceptance notification: Feb 17, 2004 Final paper due: Mar 24, 2004 Please refer to http://isca.in.tum.de for the complete call for papers and other details about the symposium. -------------------------------------------------------------------------= - ********************************************************************* 2nd CALL FOR PAPERS ********************************************************************* Workshop on Network Processors & Applications - NP3 http://www.cse.wustl.edu/NP3/ February 14-15, 2004 Madrid, Spain Held in conjunction with HPCA 10 - The 10th International Symposium on High-Performance Computer Architecture http://www.ac.uma.es/hpca10/ February 14-18, 2004 OVERVIEW As the performance and importance of digital communication networks have increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility and economy requirements, the networking industry has opted to build products around network processors. These processors are programmable yet application-specific; their designs are tailored to efficiently implement communications applications such as: routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS. The term network processor is used here in the most generic sense -- from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Network processor design is an emerging field with numerous challenges and opportunities. The goal of this workshop is to provide a forum for engineers and scientists from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. We are especially interested in attracting new or experimental techniques and approaches. IMPORTANT DATES Submissions due: November 3 Author notifications: December 22 Final papers due: January 9 TOPICS Topics of particular interest include, but are not limited to: * Architectures for network, communications, or packet processors * Network processor theory of design * Novel commercial product designs * Search engines * Benchmarking and performance analysis * Coprocessors such as CAMs and other support devices * Interfaces to high-speed packet buses and switch fabrics * Techniques for accelerating network services * Voice processing and packet telephony * Software aspects of programming processors for networking * Applications, including packet forwarding, packet classification, QoS, encryption and security, compression, etc. The workshop will consist of a keynote address, paper presentations and a panel session. In addition to academic and research contributions, product descriptions that focus on architecture (hardware or software) or performance analysis will also be considered. Attendees will receive a copy of workshop papers. SUBMISSIONS Please submit full papers (single spaced, font size 11, 1 inch margins, not exceeding 15 pages) in Adobe PDF format for review to pcrowley@cse.wustl.edu. PROGRAM COMMITTEE Alan Berenbaum, Agere Brad Calder, UCSD Andrew Campbell, Columbia University Patrick Crowley, Washington University in St. Louis Jordi Domingo, UPC (Spain) Mark Franklin, Washington University in St. Louis Jorge Garcia, UPC (Spain) Haldun Hadimioglu, Polytechnic University Marco Heddes, Transwitch Corporation Manolis Katevenis, University of Crete (Greece) Bill Mangione-Smith, UCLA Kenneth Mackenzie, Reserviour Labs John Marshall, Cisco Daniel Mlynek, EPFL (Switzerland) Peter Z. Onufryk, IDT Lothar Thiele, ETH Z=FCrich (Switzerland) Jon Turner, Washington University in St. Louis Mateo Valero, UPC (Spain) Tilman Wolf, University of Massachusetts ORGANIZERS Patrick Crowley, Washington University in St. Louis (pcrowley@cse.wustl.e= du) Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu) Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu) Peter Z. Onufryk, IDT (peter.onufryk@idt.com) NP2 at HPCA 9 (2003) http://www.cs.washington.edu/NP2/ Selected papers from NP2 and additional industry contributions will appear in Network Processor Design : Issues and Practices Volume II (Morgan Kaufmann Publishers, October 2003). NP1 at HPCA 8 (2002) http://www.cs.washington.edu/NP1/ Selected papers from NP1 and additional industry contributions appear in Network Processor Design : Issues and Practices Volume I http://www.mkp.com/books_catalog/catalog.asp?ISBN=3D1-55860-875-3 (Morgan Kaufmann Publishers, September 2002). _____________________________________________________________________ -------------------------------------------------------------------------= -- ********************************************************* * * * CALL FOR PAPERS * * * * * * The 11th Reconfigurable Architectures Workshop * * * * RAW 2004 * * * * April 26 - 27, 2004, Santa Fe, New Mexico * * * * * * SUBMISSION DEADLINE EXTENDED: October 20, 2003 * * * * http://www.ece.lsu.edu/vaidy/raw04/ * * * ********************************************************* The 11th Reconfigurable Architectures Workshop (RAW 2004) will be held at= the Eldorado Hotel Santa Fe, New Mexico on Monday, April 26, and Tuesday Apri= l 27 2004. RAW 2004 is associated with the 18th Annual International Parallel = and Distributed Processing Symposium (IPDPS 2004) and is sponsored by the IEE= E Computer Society's Technical Committee on Parallel Processing. RAW 2004 i= s one of the major meetings for researchers to present ideas, results, and on-g= oing research on both theoretical and practical advances in Reconfigurable Com= puting. The main focus of the workshop is on Run-Time & Dynamic Reconfiguration: Architectures, Algorithms, Technolo= gies Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly= ) the functionalities of its components and the interconnection between them to= suit the problem. Key to this ability is reconfiguration handling and speed. T= hough theoretical models and algorithms for them have established reconfigurati= on as a very powerful computing paradigm, practical considerations make these m= odels difficult to realize. On the other hand, commercially available devices (= such as FPGAs and new coarse-grain FPFAs) appear to have more room for exploit= ing run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essenti= al to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2004 aims to provide a forum for creative and productive interaction between all these disciplines. Topics of Interest:=20 Authors are invited to submit manuscripts of original unpublished researc= h in all areas of dynamic and run-time reconfiguration (foundations, algorithm= s, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and applications). The topics of interest include, but ar= e not limited to:=20 Models & Architectures=20 * Theoretical Models (R-Mesh, etc.)=20 * RTR Models and Systems * RTR Hardware Architectures * Optical Interconnect Models=20 * Simulation and Prototyping * Bounds and Complexity Issues=20 Algorithms & Applications=20 * Algorithmic Techniques=20 * Mapping Parallel Algorithms=20 * Distributed Systems & Networks * Fault Tolerance Issues=20 * Wireless and Mobile Systems * Automotive Applications, etc.=20 Technologies & Tools=20 * Configurable Systems-on-Chip * Energy Efficiency Issues=20 * Devices and Circuits * Reconfiguration Techniques=20 * High Level Design Methods=20 * System support=20 Submission Guidelines: Authors should submit by email an electronic version of their work by October 20, 2003 to Serge Vernalde, IMEC, Belgium (vernalde@imec.be) AND register their paper through our web-interface at http://www.ece.lsu.edu/vaidy/raw04/ All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript (not to exceed 8 p= ages of single spaced text, including figures and tables) or, in special cases= , may be a summary of relevant work. Submissions should be in pdf-format (preferred), or alternatively in Postscript (level 2) format. Authors sho= uld make sure that the submission can be viewed using ghostscript and will pr= int on standard letter size paper (8.5" x 11"). The IEEE CS Press will publish the IPDPS symposium and workshop abstracts= as a printed volume. The complete symposium and workshop proceedings will also= be published by IEEE CS Press as a CD-ROM disk. Important Dates:=20 Manuscript due: October 20, 2003=20 Notification of acceptance/rejection: November, 2003=20 Final version due: January, 2004=20 Organization: Workshop Chair: Juergen Becker, Universitat Karlsruhe (TH), Germany (becker@itiv.uni-karlsruhe.de) Program Chair: Serge Vernalde, IMEC, Belgium (vernalde@imec.be) Steering Chair: Viktor K. Prasanna, University of Southern California, US= A (prasanna@ganges.usc.edu) Publicity Chair (USA): Ramachandran Vaidyanathan, Louisiana State University, USA=20 (vaidy@ece.lsu.edu) Publicity Chair (Europe, Asia): Reiner Hartenstein, Kaiserslautern Univer= sity of Technology, Germany (reiner@hartenstein.de) Program Committee: Jeffrey Arnold, Adaptive Silicon, Inc., USA Juergen Becker, Universitat Karlsruhe (TH), Germany Neil Bergmann, University of Queensland, Australia Christophe Bobda, Universitat Erlangen-Nurnberg, Germany Don Bouldin, University of Tennessee, USA Gordon Brebner, University of Edinburgh, UK Klaus Buchenrieder, Infineon Technologies, Germany Thomas Buchner, IBM, Germany Peter Y. K. Cheung, Imperial College of Science Technology & Medicine, Lo= ndon,=20 UK Oliver Diessel, University of New South Wales, Australia Carl Ebeling, University of Washington, USA Hossam ElGindy, University of New South Wales, Australia Manfred Glesner, Darmstadt University of Technology, Germany Patrick Girard, LIRMM, Montpellier, France Steve Guccione, Quicksilver Technology, USA Herbert Gruenbacher, Vienna University of Technology, Austria Wolfram Hardt, Technische Universitat Chemnitz, Germany Reiner Hartenstein, University of Kaiserslautern, Germany Ulrich Heinkel, Lucent Technologies, Germany Mark Jones, Virginia Tech, USA Mohammed A. S. Khalid, Cadence Design Systems, USA Hyoung-Joong Kim, Kangwon National University, Korea Fabrice Kordon, Université Pierre & Marie Curie, Paris, France Rainer Kress, Infineon Technologies, Germany Markus Kuehl, Forschungszentrum Informatik (FZI), Karlsruhe, Germany Rudy Lauwereins, IMEC, Leuven, Belgium Philip Leong, Chinese University of Hong Kong, China Marnane Liam, University College, Ireland Rong Lin, State University of New York, Geneseo, USA Wayne Luk, Imperial College, UK Juergen Luka, DaimlerChrysler AG, Germany Patrick Lysaght, Xilinx, USA Malgorzata Marek-Sadowska, University of California, Santa Barbara, USA John McHenry, National Security Agency, USA Alessandro Mei, University Rome "La Sapienza", Italy Martin Middendorf, Katholische Universität Eichstätt, Germany Amar Mukherjee, University of Central Florida, USA Dietmar Meuller, Technische Universitat Chemnitz, Germany Koji Nakano, Hiroshima University, Japan Marco Platzner, Swiss Federal Institute of Technology (ETH) Zuerich, Bernard Pottier, Université de Bretagne Occidentale, France Ranjani Parthasarathi, School of Computer Science and Engineering, Anna University, Chennai, India Michel Renovell, LIRMM, France Franz Rammig, Universitat Paderborn, Germany Peter Roth, IBM, Germany Sakir Sezer, Queen's University, N. Ireland, U.K. John Schewel, Virtual Computer Corp., USA Hartmut Schmeck, Universität Karlsruhe (TH), Germany Gerard Smit, University of Twente, The Netherlands V. Sridhar, Satyam Computer Services Ltd., India Juergen Teich, Friedrich-Alexander-Universitaet Erlangen, Germany Lionel Torres, LIRMM, Montpellier, France Jim Torresen, University of Oslo, Norway Jerry L. Trahan, Louisiana State University, USA Ramachandran Vaidyanathan, Louisiana State University, USA Milan Vasilko, Bournemouth University, UK Stamatis Vassiliadis, Delft University of Technology, The Netherlands Serge Vernalde, IMEC, Belgium Martin Vorbach, PACT Informationstechnologie, Germany K. Waldschmidt, Universitat Frankfurt, Germany Norbert Wehn, University of Kaiserslautern, Germany Peixin Zhong, Lucent Technologies, USA Hans Christoph Zeidler, Universitat der Bundeswehr Hamburg, Germany -------------------------------------------------------------------------= - WEPA-1: 1st Workshop on Embedded Parallel Architectures (dragon.kayamba.com/~enric/wepa-1.htm) to be held in conjunction with the 10th International Symposium on High Performance Computer Architecture Madrid, Spain Saturday, Feb 14th, 2004 Objectives and Scope The workshop addresses the different issues encountered while architectin= g parallel systems (multi-processor, multi-threaded, hybrid) for embedded applications. The workshop papers will explore the issues at the architecture level, th= e support needed at the compiler and OS, the effort placed at the applicati= on level in porting old code to the new architectures and the tools develope= d to simulate the performance of the embedded systems. The goal of this workshop is to create a forum wherein the authors can pr= esent the issues they have encountered and the solutions they have applied in o= rder to solve the problems. Papers submitted to WEPA-1 must contain new resear= ch or improvement on previous works that have not been already presented in a p= rior conference. Major topics include, but are not limited to * Architecture * Multi-processor architectures * Multi-threaded architectures * Hybrid architectures * Speculation and prediction techniques * Parallel I/O-bound architectures * Parallel Memory-bound architectures * Low-power techniques specific for parallel architecture= s * Hardware support for synchronization of threads/process= ors * Hardware support for contention and coherency * Debugging support * Compiler and OS * Support for thread/processor synchronization * Parallelization techniques * Applications * Networking (routers, security, monitoring, storage) * Real-time (satellite, sensoring, automotive) * Multimedia (DSPs, graphics) * etc. * Performance * Performance/Cost trade-off * Architectural modeling * Trace analysis * Comparison with non-parallel architectures Workshop Co-chairs * Mario Nemirovsky (Kayamba, Inc.) mario@kayamba.com * Jean-Luc Gaudiot (UC Irvine) gaudiot@uci.edu * Enric Musoll (Kayamba, Inc.) enric@kayamba.com Important Deadlines * Paper Submission: Oct 1st, 2003, *** Extended to Nov 23rd '03 *** * Author Notification: Nov 14th, 2003, *** Extended to Dec 22nd '03 *= ** * Camera-ready Papers: Dec 19th, 2003, *** Extended to Jan 12th '04 *= ** Questions and Submission Procedure * Please submit your manuscripts and questions to enric@kayamba.com * Manuscripts should not exceed 8 single-column double-spaced pages, = and they should be in pdf format only. * The submitted file must contain an additional cover page detailing complete author information, including contact author email. * Final version for the accepted papers will be allowed to have 6 pag= es in usual IEEE two column conference proceedings format. -------------------------------------------------------------------------= - =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D High Availability and Performance Computing Workshop (HAPCW) 2003 Eldorado Hotel - Santa Fe, New Mexico October 27, 2003 HAPCW 2003 will be held on October 27, 2003 in conjunction with the 2003 Los Alamos Computer Science Institute Symposium 2003 (LACSI2003), at the Eldorado Hotel in Santa Fe, New Mexico. High Availability (HA) Computing has long been played a critical role in industry mission critical applications. On the other hand, High Performance Computing (HPC) has equally been a significant enabler to the R&D community for their scientific discoveries. With combination of HA and HPC, together will clearly lead to even more benefits to both industry, academic and research entities. HAPCW2003 will provide an important venue for discussing state-of-art and on-going research and development in HAPC. In addition to the presentation of reviewed papers, the workshop will include a panel discussion of relevant topics. Topics of interest are those relevant to HAPC including the following: ---------------------------------------------------------------------- * High Availability (Reliability) and Performance Computing Analysis. * Architecture, Middleware and Tools supporting HAPC. * High Availability and Performance Cluster Computing. * Experiences creating HAPC environments and current project status. * Self-healing, Fault Prevention, Detection and Recovery, Fault Tolerance= , and Autonomic Computing. * Configuration, Resource and Fault Management. Submission Guidelines: ---------------------- Original, unpublished work is required. Extended abstracts are not to exceed 2 pages (two columns, single space, 10 point font), including tables and illustrations. Accepted contributions will be published in the proceedings website and CD which will be available at the workshop. The final manuscript shall be a maximum of 6 IEEE style pages in Camera-Ready. Please send all extended abstracts by email, in Postscript or PDF format to: box@latech.edu Schedule: --------- September 22, 2003 Extended Abstract Due September 26, 2003 Acceptance Notification October 17, 2003 Final paper due (electronic copy) October 27, 2003 Workshop (HAPCW) at LACSI Workshop Co-Chairs: ------------------- Stephen L. Scott Chokchai (Box) Leangsuksu= n Computer Science & Mathematics Division Computer Science Departmen= t, Oak Ridge National Laboratory Louisiana Tech University Oak Ridge, TN 37831, USA Ruston, LA 71272, USA scottsl@ornl.gov box@latech.edu Program Committee: ------------------ Chris Cunningham (Louisiana Tech University) Ibrahim Haddad (Ericsson, CA) Chokchai "Box" Leangsuksun (Louisiana Tech University) Benoit des Ligneris (Sherbrooke University) Stephen L. Scott (Oak Ridge National Laboratory) Web sites: ---------- HAPCW http://cenit.latech.edu/hapcw2003 October 27, 2003 LACSI http://lacsi.lanl.gov/symposium October 27-29, 2003 --=20 -------------------------------------------------------------------------= - -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D= -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Call For Papers =20 HiCOMB 2004 3rd International Workshop On High Performance Computational Biology http://www.hicomb.org/ =20 held in conjunction with the International Parallel and Distributed Processing Symposium www.ipdps.org April 26, 2004 Eldorado Hotel, Santa Fe, NM -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D= -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Computational Biology is fast emerging as an important discipline for academic research and industrial application. The large size of biological data sets, inherent complexity of biological problems and the ability to deal with error-prone data all result in large run-time and memory requirements. The goal of this workshop is to provide a forum for discussion of latest research in developing high-performance computing solutions to problems arising from molecular biology. We are especially interested in parallel algorithms, memory- efficient algorithms, large scale data mining techniques, and design of high-performance software. The workshop will feature contributed papers as well as invited talks from reputed researchers in the field. Topics of interest include but are not limited to: * Bioinformatic databases * Computational genomics * Computational proteomics * DNA assembly, clustering and mapping * Gene expression and microarrays * Gene identification and annotation * Parallel algorithms for biological analysis * Parallel architectures for biological applications * Molecular evolution * Molecular sequence analysis * Phylogeny reconstruction algorithms * Protein structure * String data structures and algorithms Submission Guidelines: ---------------------- Papers reporting on original research (both theoretical and experimental) in all areas of bioinformatics and computational biology are sought. Surveys of important recent results and directions are also welcome. To submit a paper, send a postscript or PDF copy of the paper by email to the workshop's Program Chair, Prof. Dan C. Marinescu, . The paper should not exceed 12 single-spaced pages (US Letter or A4 size) in 11pt font or larger. All papers will be reviewed. IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press on CD-ROM and will also be available in the IEEE Digital Library. Authors of selected papers from the workshop will be invited to submit extended versions of their papers for publication in the journal Concurrency and Computation: Practice and Experience. Important Dates: ---------------- December 1, 2003 Workshop paper due December 31, 2003 Author Notification January 23, 2004 Camera-ready Paper Due Workshop Co-Chairs: ------------------- Prof. Srinivas Aluru Prof. David A. Bader =20 Electrical & Computer Engg. Electrical & Computer Engg. Iowa State University University of New Mexico =20 3218 Coover Hall Albuquerque, NM 87131 USA =20 Ames, IA 50014 USA Email: dbader@ece.unm.edu=20 Email: aluru@iastate.edu Tel: 505-277-6724 =20 Tel: 515-294-3539 Program Chair: -------------- Dan C. Marinescu Computer Science Department University of Central Florida 4000 Central Florida Boulevard Orlando Florida, 32816, USA Email: dcm@cs.ucf.edu http://www.cs.ucf.edu/~dcm Phone: +1 407 823 4860 FAX: +1 407 823 5419 =20 Program Committee: ------------------ Prof. Alberto Apostolico Computer Sciences Department Purdue University West Lafayette, IN, 47907 Email: axa@cs.purdue.edu http://www.cs.purdue.edu/people/axa Phone: +1.765.494.6015 Prof. Concettina Guerra Dip. Ingegneria dell'Informazione Universita'di Padova via Gradenigo 6a, 35100, Padova, Italy Email: guerra@dei.unipd.it http://www.dei.unipd.it/~guerra Phone: +39 049 827 7933 =20 Prof. Wojciech Szpankowski Computer Sciences Department Purdue University =20 West Lafayette, IN, 47907 Email: spa@cs.purdue.edu http://www.cs.purdue.edu/people/spa Phone: +1.765.494.6703 =20 --=20 -------------------------------------------------------------------------= - Call For Papers Workshop on Communication Architecture for Clusters (CAC '04) To be held in Conjunction with Int'l Parallel and Distributed Processing Symposium (IPDPS '04) Santa Fe, New Mexico Eldorado Hotel, April 26-30, 2004=20 -------------------------------------------------------------------------= ----- web page http://www.cis.ohio-state.edu/~cac -------------------------------------------------------------------------= ----- Call For Papers THEME: The availability of commodity PCs/workstations and high-speed networks (L= ocal=20 Area Networks and System Area Networks) at low prices enabled the develop= ment of=20 low-cost clusters. These clusters are being targeted for support of tradi= tional=20 high-end computing applications as well as emerging applications, especia= lly=20 those requiring high-performance servers. Designing high-performance and=20 scalable clusters for these emerging applications requires design and=20 development of high-performance communication and I/O subsystems, low-ove= rhead=20 programming environment support and support for Quality of Service (QoS).= New=20 standards such as InfiniBand Architecture (IBA) and PCI Express AS, and=20 availability of high-speed networking products (Myrinet, Quadrics, IBA 4X= , and=20 10GigEthernet) are providing exciting ways to design high-performance=20 communication and I/O architectures for clusters.=20 A large number of research groups from academia, industry, and research l= abs are=20 currently engaged in the above research directions. The goal of this work= shop is=20 to bring together researchers and practitioners working in the areas of=20 communication, I/O, and architecture to discuss state-of-the-art solution= s as=20 well as future trends for designing scalable, high-performance, and=20 cost-effective communication and I/O architectures for clusters.=20 The first three workshops in this series (CAC '01, CAC '02, and CAC '03) = were=20 held in conjunction with IPDPS conferences, and they were very successful= . The=20 CAC '04 workshop plans to continue this tradition.=20 TOPICS OF INTEREST: Topics of interest for the workshop include but are not limited to: Router/switch, network, and network-interface architecture for supporting= =20 efficient point-to-point communication, collective communication, and I/O= at=20 intra-cluster and inter-cluster levels.=20 Design, development, and implementation of low-level communication and I/= O=20 protocols (GM, TCP/IP, VAPI, SDP, DAPL, SRP, iSCSI, RDMA over IP, etc) on= =20 different networking and interconnect technologies (such as Myrinet, 10Gi= gabit=20 Ethernet, InfiniBand, Quadrics, TCP Offload Engine, etc.).=20 High-performance implementation of different programming layers (Message=20 Passing Interface (MPI), Distributed Shared Memory such as TreadMarks,=20 Get/Put, Global Arrays, sockets, etc.) and File Systems (such as PVFS and= =20 DAFS).=20 Communication and architectural issues related to switch organization, fl= ow=20 control, congestion control, routing and deadlock-handling, load balancin= g,=20 reliability, and QoS support.=20 Strategies, algorithms, and protocols for management of communication=20 resources, including topology discovery, hot update/replacement of compon= ents,=20 dynamic reconfigurations, etc.=20 Performance evaluation and tools for different application areas, includi= ng=20 interprocessor communication and I/O, etc.=20 Results of both theoretical and practical significance will be considered= .=20 PROCEEDINGS: The proceedings of this workshop will be published together with the proc= eedings=20 of other IPDPS '04 workshops by the IEEE Computer Society Press.=20 PAPER SUBMISSIONS: We are planning a purely web submission and review process. Authors are=20 requested to submit papers (in PDF format) not exceeding 10 single-spaced= pages,=20 including abstract, five key words, contact address, figures, and referen= ces.=20 Detailed instructions on web submissions will be available soon.=20 Note: the PDF file must be viewable using the ``acroread'' tool. It is al= so=20 important, when creating your PDF file, to use a page size of 8.5x11 inch= es=20 (LETTER sized output not A4), since an A4 sized page may be truncated on = a=20 LETTER sized printer. =20 SCHEDULE: =20 Title and Abstract: October 30, 2003=20 Paper submission: November 3, 2003=20 Notification of acceptance: December 19, 2003=20 Camera-ready due: January 23, 2004=20 WORKSHOP CO-CHAIRS: Dhabaleswar K. Panda (Ohio State), Jose Duato (Tech. Univ. of Valencia, S= pain),=20 and Craig Stunkel (IBM TJ Watson Research Center)=20 PROGRAM COMMITTEE:=20 =09 Bulent Abali (IBM TJ Watson)=20 Mohammad Banikazemi (IBM TJ Watson)=20 Angelos Bilas (Univ. of Toronto, Canada)=20 Alan Benner (IBM)=20 Ron Brightwell (Sandia National Lab)=20 Darius Buntinas (Argonne National Lab)=20 Toni Cortes (UPC, Spain)=20 Wu-Chun Feng (Los Alamos National Lab)=20 Jose Flich (Tech. Univ. of Valencia, Spain)=20 Mitchell Gusat (IBM, Zurich)=20 Mark Heinrich (Univ. of Central Florida)=20 Manolis G.H. Katevenis (FORTH and Univ. of Crete, Greece)=20 Nectarios G. Koziris (National Technical Univ. of Athens, Greece)=20 Mario Lauria (Ohio State)=20 Olav Lysne (Univ. of Oslo, Norway)=20 Arthur (Barney) Mccabe (Univ. of New Mexico)=20 Pankaj Mehra (HP)=20 Shubu Mukherjee (Intel)=20 Jarek Nieplocha (Pacific Northwest National Lab)=20 Scott Pakin (Los Alamos National Lab)=20 Fabrizio Petrini (Los Alamos National Lab)=20 Greg Pfister (IBM)=20 Timothy Pinkston (Univ. of Southern California)=20 Wolfgang Rehm (Tech. Univ. of Chemnitz, Germany)=20 Antonio Robles (UPV, Spain)=20 Tom Rokicki (Instantis)=20 Reza Rooholamini (Dell)=20 Evan Speight (Cornell Univ.)=20 Thomas M. Stricker (ETH, Zurich, Switzerland)=20 Peter Varman (NSF and Rice Univ.)=20 Pete Wyckoff (Ohio Supercomputer Center)=20 Mazin Yousif (Intel)=20 PUBLICITY COORDINATORS: Darius Buntinas (Argonne National Lab) and Nectarios G. Koziris (National= =20 Technical Univ. of Athens, Greece)=20 ADDITIONAL INFORMATION: For further questions, send e-mail to cac@cis.ohio-state.edu.=20 -------------------------------------------------------------------------= - ******************** CALL FOR PAPERS ********************** =20 Workshop on Interaction between Compilers and Computer Architectures (Interact 8) =20 http://api.ece.uic.edu/workshop/interact.htm February 15, 2004 Madrid, Spain =20 Held in Conjunction with HPCA 10 http://www.ac.uma.es/hpca10/ =20 IMPORTANT DATES =20 Submissions due: November 23, 2003 Acceptance notification by December 22, 2003 Final version due by January 12, 2004 =20 TOPICS * Code Generation and scheduling *Memory, Cache, and Register Management *Dynamic Recompilation *Speculative and predicated Execution *Parallelism Enhancement and Exploitation *Efficient I/O operations *Experiences in Optimizing Compiler *Run-time Support *Task Synchronization and Scheduling *Code Generation for Low Power *Support for Secure/Trusted Computing =20 Program Committee Chair: Wei Hsu (U. Minnesota) =20 Program Committee: Sangyeun Cho (Samsung Electronic) Dan Conners (U. Colorado) Antonio Gonzalez (UPC Spain) Rick Hank (Hewlett Packard) Allan Knies (Intel) Gyungho Lee (UI-Chicago) Sally McKee (Cornell University) Sanjay Patel (UI-Urbana-Champaign) Eric Rotenberg (NC State) Zhao Zhang (Iowa State University) =20 Formal post-workshop proceedings will be published by IEEE Computer Society Press. An informal collection of the papers to be presented will be distributed at the workshop. Questions regarding the post-workshop proceedings should be forwarded to ghlee@ece.uic.edu. =20 For more details, visit http://api.ece.uic.edu/workshop/interact.htm =20 -------------------------------------------------------------------------= - * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20